Memory consistency models using constraints ozgur akgun. Two techniques to enhance the performance of memory. Cs 152 computer architecture and engineering cs252. Memory consistency models for high performance distributed computing by victor luchangco s. Based on the material prepared by arvind and krste asanovic. For example, on the program above, sequential consistency forbids any ordering that results in printing 00, but allows some orderings that print 01 and 11. Memory consistency model mcm determines its meaning by defining the legal ordering of memory references issued by some processor, as observed by other processors in the system 4, 5. Answer is determined by the memory consistency model of the system determines the order in which shared memory accesses from different threads can appear to execute. Allowing reads to bypass writes is crucial for achieving good performance, and all relaxed memory models processor consistency, weak consistency, release consistency, etc. The goal of this primer is to provide readers with a. Basically, we identify the characteristics that are inherent to all memory consistency models and the characteristics that are model specific. A memory consistency model or a memory model for a sharedmemorymultiprocessor system is a formal speci.
Memory consistency model memory model formal specification of how shared memory will appear to programmers consistency restricts values that can be returned by a read during execution why memory consistency models. You can think of it as a contract between the processor architecture hardware and the software r. The motivation for dsm is that it allows a shared memory programming model to be employed, which has some advantages over messagebased models. Programming for different memory consistency models. An mp is sc if exec result is same as if all procs were in some sequence. In this lecture, we will cover some of them in more detail. If developers write unsynchronized code assuming certain instruction orderings or memory visibilities which are not in line with the shared memory consistency model, then code can be buggy. The simplest and most intuitive model for programmers, sequential consistency, restricts the use of many performanceenhancingoptimizations exploited by uniprocessors. It defines how memory will appear to a programmer by placing restrictions on the values that can be returned by a read of a memory location. Shared memory caches, cache coherence and memory consistency models references computer organization and design. Slow consistency is a weaker model than pram and cache consistency. Eliminate gap between expected behavior behavior supported by a. A study of a software cache implementation of the openmp. We aim to describe memory consistency models in a way that most computer professionals would understand.
In this paper, we explore shared memory, memory consistency models and mechanisms for differentiating memory operations. The memory consistency model of a system affects performance, programmability, and portability. Classes of consistency models relaxed consistency improves shared memory access performance while ensuring correctness to a specified consistency model any memory consistency model which is weaker than sequential consistency 1. A study of a software cache implementation of the openmp memory model for multicore and manycore architectures chen chen1, joseph b manzano 2, ge gan2, guang r. Pai, student member, ieee, and parthasarathy ranganathan, student member, ieee invited paper the memory consistency model of a shared memory system. The memory consistency model or memory model of a shared memory multiprocessor system in.
Request pdf compiler optimisations and relaxed memory consistency models modern multiprocessors architectures and programming languages exhibit weakly consistent memories. A tutorial introduction to the arm and power relaxed memory models luc maranget inria susmit sarkar. Intuitively, a read should return the value of the last write to the same memory location. This is important if the performanceenhancing features being incorporated by system designers are to be correctly and widely used by programmers. Compilers basically, what we want to do is develop models. Operational characterization of weak memory consistency models. Tso is a relaxation of the sc model and thus will allow for more behaviour than sc. Such interfaces are called memory consistency models and determine which relaxations or optimizations are possible and in which way the system behaves di erent to a sequential consistent one. Adve is with the department of electrical and computer engineering, rice university, houston, texas 772511892. Lightweight objectoriented shared variables for cluster computing in java.
Shared memory consistency models for traditional cpus have been well studied over the years 28 and continues to be. Writes performed by a process are immediately visible to that process. Consistency models are not about dependent memory operations in a single processorsinstruction stream these are respected even by processors that reorder instructions. Were well aware of and on top of the issues we caught the spec bugs well before theyll actually affect any implementations in practice. The second part discusses the issues that arise due to weakening memory consistency. Defined in so called memory consistency models this is really a contract between the hardware, the compiler, and the programmer i. Lots of consistency model defined by a wide variety of source including architecture system, application programmer etc. Only if interested in much more detail on cache coherence. To write correct and efficient shared memory programs, programmers need a precise notion of how memory behaves with respect to read and write operations from multiple processors s. When combined, the above techniques alleviate the limitations imposed by a consistency model on buffering and pipelining of memory accesses, thus signi. Eliminate gap between expected behavior behavior supported by a system. Sequential consistency sc 11 is the most commonly used memory model since.
Memory consistency models for sharedmemory multiprocessors. This paper is motivated by the desire to provide an ef. Compilers basically, what we want to do is develop models where one operation. Most of this work was performed while sarita adve was at the. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept uptodate. Consistency definitions provide rules about loads and stores or memory reads and writes and how they act upon memory. The consistency model defines the ordering of writes and reads to different memory locations the hardware. Litmus tests for comparing memory consistency models. The relation between the processors memory consistency model and the coherence protocol has traditionally been abstracted to the point where each subsystem considers the other as a black box 41. Shared memory correctness is defined by the memory consistency model, which formally specifies how the memory must appear to the programmer 1. In order to prove the generality of our framework, we. Designing memory consistency models for sharedmemory.
Complexity of the memory model arises out of the desire to do things quickly if we are content with slow and safe, things can be pretty straightforward. Operations of each proc appear in this sequence in order specified by. Essentially, a memory consistency model restricts the values that a read can return. Recent advances in memory consistency models for hardware shared memory systems sarita v. A primer on memory consistency and cache coherence. In addition to digital equipments support, the author was partly supported by darpa contract n00039. Memory consistency models for shared memory multiprocessors kourosh gharachorloo december 1995 also published as stanford university technical report csltr95685. Gao, and vivek sarkar3 1 tsinghua university, beijing 84, p. We have found instances of such assumptions in real world code. A memory consistency model is a set of rules that governs how memory systems will process memory operations load store from multiple processors. Adve kourosh gharachorloo september 1995 also publised as rice university ece technical report 9512.
Memory consistency models david mosberger tr 9311 abstract this paper discusses memory consistency models and their in. In slow consistency, if a process reads a value previously written to a memory location, it cannot subsequently read any earlier value from that location. Defining uniform and hybrid memory consistency models on. A tutorial introduction to the arm and power relaxed. A memory consistency model which we often just call a memory model defines the allowed orderings of multiple threads on a multiprocessor. A consistency model is the definition of when modifications to data may be seen at a given processor. Compiler optimisations and relaxed memory consistency models. Location consistency a new memory model and cache consistency protocol. Definitions memory consistency model formal specification of mem system behavior to programmer program order the order in which memory operations appear in program sequential consistency sc. In particular, we discuss the interactions between a weakened memory system and the software using it. The memory consistency model of a shared memory multiprocessor for mally specifies how the memory system will appear to the programmer. A simple and general definition of memory consistency model is proposed. Memory consistency models using constraints 3 this paper will contain the sequential consistency sc model which we discuss in section 2.